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Updated: 12/29/21

Persistent Memory Systems

  1. Andrei, Mihnea, et al. "SAP HANA adoption of non-volatile memory." Proceedings of the VLDB Endowment 10.12 (2017): 1754-1765.
  2. Caulfield, Adrian M., et al. "Moneta: A high-performance storage array architecture for next-generation, non-volatile memories." 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture. IEEE, 2010.
  3. Chakrabarti, Dhruva R., Hans-J. Boehm, and Kumud Bhandari. "Atlas: Leveraging locks for non-volatile memory consistency." ACM SIGPLAN Notices 49.10 (2014): 433-452.
  4. Condit, Jeremy, et al. "Better I/O through byte-addressable, persistent memory." Proceedings of the ACM SIGOPS 22nd symposium on Operating systems principles. 2009.
  5. Dulloor, Subramanya R., et al. "System software for persistent memory." Proceedings of the Ninth European Conference on Computer Systems. 2014.
  6. Hoseinzadeh, Morteza, and Steven Swanson. "Corundum: statically-enforced persistent memory safety." Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems. 2021.
  7. Kadekodi, Rohan, et al. "SplitFS: Reducing software overhead in file systems for persistent memory." Proceedings of the 27th ACM Symposium on Operating Systems Principles. 2019.
  8. Kannan, Sudarsun, Ada Gavrilovska, and Karsten Schwan. "pvm: Persistent virtual memory for efficient capacity scaling and object storage." Proceedings of the Eleventh European Conference on Computer Systems. 2016.
  9. Kolli, Aasheesh, et al. "Delegated persist ordering." 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2016.
  10. Lee, Se Kwon, et al. "Recipe: Converting concurrent DRAM indexes to persistent-memory indexes." Proceedings of the 27th ACM Symposium on Operating Systems Principles. 2019.
  11. Liu, Sihang, et al. "PMTest: A fast and flexible testing framework for persistent memory programs." Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems. 2019.
  12. Neal, Ian, Andrew Quinn, and Baris Kasikci. "Hippocrates: healing persistent memory bugs without doing any harm." Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems. 2021.
  13. Pelley, Steven, Peter M. Chen, and Thomas F. Wenisch. "Memory persistency." 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA). IEEE, 2014.
  14. Qureshi, Moinuddin K., Vijayalakshmi Srinivasan, and Jude A. Rivers. "Scalable high performance main memory system using phase-change memory technology." Proceedings of the 36th annual international symposium on Computer architecture. 2009.
  15. Qureshi, Moinuddin K., et al. "Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling." 2009 42nd Annual IEEE/ACM international symposium on microarchitecture (MICRO). IEEE, 2009.
  16. Ren, Jinglei, et al. "ThyNVM: Enabling software-transparent crash consistency in persistent memory systems." 2015 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2015.
  17. Venkataraman, Shivaram, et al. "Consistent and Durable Data Structures for Non-Volatile Byte-Addressable Memory." FAST. Vol. 11. 2011.
  18. Volos, Haris, Andres Jaan Tack, and Michael M. Swift. "Mnemosyne: Lightweight persistent memory." ACM SIGARCH Computer Architecture News 39.1 (2011): 91-104.
  19. Xu, Jian, and Steven Swanson. "{NOVA}: A log-structured file system for hybrid volatile/non-volatile main memories." 14th {USENIX} Conference on File and Storage Technologies ({FAST} 16). 2016.
  20. Yang, Jian, et al. "An empirical guide to the behavior and use of scalable persistent memory." 18th {USENIX} Conference on File and Storage Technologies ({FAST} 20). 2020.
  21. Zhang, Yiying, et al. "Mojim: A reliable and highly-available non-volatile memory system." Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems. 2015.
  22. van Renen, Alexander, et al. "Managing non-volatile memory in database systems." Proceedings of the 2018 International Conference on Management of Data. 2018.

Computer Architecture

  1. Blem, Emily, Jaikrishnan Menon, and Karthikeyan Sankaralingam. "Power struggles: Revisiting the RISC vs. CISC debate on contemporary ARM and x86 architectures." 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA). IEEE, 2013.
  2. Jouppi, Norman P. "Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers." ACM SIGARCH Computer Architecture News 18.2SI (1990): 364-373.
  3. Mahlke, Scott A., et al. "A comparison of full and partial predicated execution support for ILP processors." Proceedings of the 22nd annual international symposium on Computer architecture. 1995.
  4. Moore, Gordon E. "Cramming more components onto integrated circuits." Proceedings of the IEEE 86.1 (1998): 82-85.
  5. Moshovos, Andreas, et al. "Dynamic speculation and synchronization of data dependences." Proceedings of the 24th annual international symposium on Computer architecture. 1997.
  6. Naffziger, Samuel, et al. "Pioneering Chiplet Technology and Design for the AMD EPYC™ and Ryzen™ Processor Families: Industrial Product." 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). IEEE, 2021.
  7. Nickolls, John, and William J. Dally. "The GPU computing era." IEEE micro 30.2 (2010): 56-69.
  8. O’Connor, Mike, et al. "Fine-grained DRAM: Energy-efficient DRAM for extreme bandwidth systems." 2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2017.
  9. Pugsley, Seth H., et al. "Sandbox prefetching: Safe run-time evaluation of aggressive prefetchers." 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA). IEEE, 2014.
  10. Seznec, André, et al. "Design tradeoffs for the Alpha EV8 conditional branch predictor." ACM SIGARCH Computer Architecture News 30.2 (2002): 295-306.
  11. Sohi, Gurindar S. "Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers." IEEE transactions on computers 39.3 (1990): 349-359.
  12. Sorin, Daniel J., Mark D. Hill, and David A. Wood. "A primer on memory consistency and cache coherence." Synthesis lectures on computer architecture 6.3 (2011): 1-212.
  13. Tullsen, Dean M., et al. "Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor." Proceedings of the 23rd annual international symposium on Computer architecture. 1996.
  14. Yan, Mengjia, et al. "Invisispec: Making speculative execution invisible in the cache hierarchy." 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2018.
  15. Yeager, Kenneth C. "The MIPS R10000 superscalar microprocessor." IEEE micro 16.2 (1996): 28-41.